Memory circuits are well known, and include an array of memory cells, each capable of storing a bit of information. In order to appropriately access a desired word of information, comprising a plurality of bits, appropriate row decoder/driver circuits are used which select appropriate row lines for access. Similarly, column accessing circuitry is often employed to select an appropriate number of bits within the row for output.
FIG. 1 is a block diagram of a typical flash memory circuit including a memory array 101 having a plurality of memory cells such as memory cell 101-N-M. Address circuitry 104 applies row information to row decoder 102 defining which of the N rows of memory array 101 is to be selected for reading or writing. Similarly, column decoder 103 receives address information defining which one or ones of the M columns of memory array 101 are to be selected. Data read from or to be applied to memory array 101 is stored in data buffer 105.
Typical memory devices operate between ground (0 volts) and a positive supply of voltage of approximately 5 volts. However, memory devices which are capable of being programmed often utilize supply voltages in excess of these voltages. For example, a typical non-volatile flash EPROM memory might use 0 and 5 volt supplies during a normal reading operation, but require a voltage of approximately 12 volts during programming and a voltage of approximately -12 volts during erasure. Modern memory devices include on chip circuitry to generate these voltages in excess of normal (and externally applied) supply voltage levels. However, it is imperative that the memory devices be fabricated in order to withstand any breakdown failures in the path which applies these high voltage levels to the memory cells being programmed or erased. Thus, referring to FIG. 1, which is an exemplary block diagram of a typical memory circuit, row decoder 102 is capable of withstanding the high voltages applied by row decoder 102 to memory cell array 101 during programming and erasure.
In order to provide circuitry which is capable of withstanding these high voltages, one technique is to utilize a triple-well CMOS structure such as described in "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode," Jinbo, et al., IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992, pgs. 1547-1553. As described by Jinbo et al., peripheral N channel and P channel transistors are formed in a conventional manner, and memory cell transistors are formed in a P well which in turn is formed with an N well within a P type substrate, thereby forming a "triple-well" CMOS structure. Similarly, negative voltage N channel transistors are formed in a separate one or more triple-well structures. This allows transistors which are subjected to high voltages to be properly isolated and capable of avoiding breakdown during the presence of high voltage differentials.
Other examples of prior art triple-well CMOS memory devices are described in "New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories", Miyawaki, et al., IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, April 1992, pages 583-588, and "5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", A. Umezawa, et al , IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992.
TABLE 1 __________________________________________________________________________ (FIG. 2) Signal (Volts) P well N well blkx rx rbx WL (rsx) (Vpp) Mode Sel Des Sel Des Sel Del Sel Des Sel Des Sel Des __________________________________________________________________________ Read 0 5 5 0 0 5 5 0 0 0 5 5 Program 0 12 12 0 0 12 12 0 0 0 12 12 Erase 5 -12 5 5 -12 -12 -12 5 -12 -12 5 5 __________________________________________________________________________
FIG. 2 is a schematic diagram of one example of a prior art row driver capable of withstanding high voltages applied during programming and erasure, with the operation of the circuit of FIG. 2 shown in Table 1. As shown in FIG. 2, row driver circuit 200 includes a pull up transistor 207 formed in N well 210 tied to Vpp, and pull down transistors 208 and 209 formed within P well 211 tied to rsx. When row driver circuit 200 is used in a triple-well CMOS structure, it receives a block select signal blkx on lead 201, which is capable of selecting a desired block, containing a plurality of rows, of the memory array. Row pre-decode signals rx and rsx are applied to leads 202 and 203, respectively, to be used with block select signal blkx during reading and programming to select a desired row by applying the appropriate signal on word line 205. Note that during erasure, row pre-decode signals rx and rsx are fixed voltages, as an entire block, containing a plurality of rows, is erased simultaneously. As shown in Table 1, it is seen that during reading only 0 and 5 volts are applied to row decoder 200 and thus the memory array. However, during programming, a high voltage of 12 volts is applied at appropriate times, and during erasure a -12 volts is applied at appropriate times. Thus, the circuit of FIG. 2, if it is to be applied to a high voltage system, must include transistors 207, 208 and 209 fashioned as high voltage devices, for example by utilizing a thick gate oxide and particular care in junction formation to prevent breakdown from occurring given the voltage differential of up to approximately 18 volts. This requires additional fabrication limitations and steps, adding to the cost of the fabrication process. Accordingly, it has been determined that utilizing a typical row decoder and operating voltage levels requires extra care and expense, which is, of course undesirable.